The present invention relates to integrated circuits. More particularly, the present invention relates to novel and cost-effective methods of encapsulating integrated circuit (IC) assemblies that are either thermally or electrically and thermally enhanced.
Encapsulated integrated circuits are known. In an encapsulated integrated circuit, the integrated circuit die is encapsulated in a mold compound, e.g., plastic, accessible through pins external to the molded plastic body. The pins themselves are typically part of a conventional leadframe, which are electrically bonded to bonding pads on the die prior to encapsulation.
As is well known, the integrated circuit die generates an appreciable amount of heat during operation. If the generated heat is not adequately vented and an excessive amount of heat is retained, heat-related damages to the integrated circuit may occur over time. To remove heat from an integrated circuit die, it is customary to thermally enhance the performance of the finished IC by attaching the die to a thermally conductive heat sink formed of, for example, copper, ceramic, or other suitable thermally conductive materials.
FIG. 1 illustrates an integrated circuit assembly of a conventional thermally-enhanced (TE) integrated circuits. The IC assembly of FIG. 1 is said to be thermally enhanced because its die is attached to a heat sink to effectuate heat removal. Referring now to FIG. 1, an integrated circuit die 10 is electrically insulated from and attached to the top side of a thermally conductive heat sink 12, which is shown to be relative bulky to facilitate efficient heat transfer. Thermally conductive heat sink 12 is preferably dimensioned so that its bottom end is exposed to the ambient environment after encapsulation to facilitate efficient heat removal from the IC die.
Bonding fingers 14 of a conventional leadframe 16 are also electrically insulated from and attached to the outer margins of thermally conductive heat sink 12 at its top side. Bonding wires 18 couple individual ones of bonding fingers 14 to bonding pads disposed at the top side of die 10 to form conduction paths to and from die 10.
As in the case of a conventional quad flat package (QFP), the bulky thermally conductive heat sink 12, its attached die 10, and bonding wires 18 are encapsulated in a mold cavity formed between the two cavity halves 20 and 22 of mold 24. Pressured molten mold material formed of, for example, thermally set plastic, is injected into the two mold cavity halves, usually at a corner of mold 24 via a port or a gate that is either coplanar with leadframe 16, in a top cavity half 20 as shown in FIG. 1, or in lower cavity half 22 (not shown). In FIG. 1, the pressured molten mold material enters the top cavity half 20 of the mold and flows over the top surface of the die, through the spaces between the bonding fingers 14 of leadframe 16 into the bottom cavity half 22 of the mold cavity. In the bottom cavity half, some of the molten mold material flows around heat sink 12 to substantially fill up bottom cavity half 22. Any gas that was present within the mold cavity is ideally expelled through air vents, of which vents 26 and 27 are exemplary. Preferably, there are air vents in both upper cavity half 20 and lower cavity half 22 as shown in FIG. 1.
With reference to FIG. 1, the arrows indicate the flow of mold material through the top cavity half and bottom cavity half of mold 24. Ideally, the molten mold material should fill up the top and bottom cavity halves of mold 24 substantially simultaneously to avoid plugging up vent 26 and trap air inside the cavity halves. This is because the trapped air creates voids, or pinholes, in the body of the finished IC.
However, the presence of heat sink 12 unbalances the flow of molten mold material by reducing the flow cross-section area in lower cavity half 22. Since the flow of mold material in upper cavity half 20 is relatively unimpeded, this causes the molten mold material in the upper cavity half of the mold to reach air vent 26 first, thereby essentially "plugging-up" the air vent. Any gas remaining in the bottom cavity half of the mold is then trapped, unable to exhaust through vent 26. As stated, this trapped air becomes pinholes, also known as blow holes or voids, in the body of the finished IC. A typical pinhole 28 is shown in FIG. 1.
The presence of pinhole 28 represents a defect in the finished IC and is often the cause for rejecting it. This is because pinhole 28 may allow ambient moisture and contaminants to reach die 10 and/or bonding fingers 14, possibly shorting out the circuitries and/or corroding the electrical contacts.
The presence of heat sink 12 also unbalances the amount of molten mold material in the two cavity halves, with the top cavity half having substantially more mold material than the bottom cavity half. As is known, molten mold materials experience shrinkage when they cool. As a consequence, the top half of the finished IC, having more mold material, tends to shrink more than the bottom half. The finished IC may warp, leading to mechanical stress and failure.
The above mentioned pinhole formation and warpage problems also affect other types of IC's as well. To facilitate discussion, FIG. 2A shows a prior art and known electrically and thermally enhanced (ETE) IC assembly, typically packaged in a quad flat pack (ETEQFP). A die 50 of ETE assembly 52 is attached to the top surface of a thermally conductive heat sink 54 using an electrically conductive adhesive such as silver epoxy or other similarly suitable adhesives. Thermally conductive heat sink 54 is preferably dimensioned so that its bottom end is exposed to the ambient environment after encapsulation to facilitate efficient heat removal from the IC die.
Die 50 is disposed in an annular opening of a wafer board 56, with the outer edges of the upper surface of heat sink 54 attached to and preferably insulated from the underside of wafer board 56. To improve mechanical integrity, wafer board 56 may optionally include a groove 58 into which heat sink 54 partially protrudes (as shown in FIG. 2A).
Bonding pads 62 at the top surface of die 50 electrically couple the die circuitries with wires 64, which are in turn electrically coupled to conducting leads running along top surface 60 of wafer board 56. These conducting leads are in turn electrically coupled to inwardly-extending fingers 66 of a leadframe 68. In the ETE assembly of FIG. 2A, heat sink 54 and wafer board 56 enhance the performance of the finished IC both thermally and electrically.
To discuss the electrical enhancements provided by the wafer board, FIG. 2B shows a cross-section view of a representative wafer board, such as wafer board 56 of FIG. 2A. For simplicity of illustration, wafer board 56 of FIG. 2B is shown without optional groove 58, whose function is, as mentioned earlier, primarily mechanical. Wafer board 56 preferably comprises a multilayer board, having alternating layers of a ground plane 70, a Vdd plane 72, a ground I/O plane 74, a Vdd I/0 plane 76, and a signal plane 78 sandwiched between insulating layers 80, 82, 84, and 86. Vias 88 and 90 electrically couple ground I/O plane 74 with ground plane 70 and Vdd I/O plane 76 with Vdd plane 72. The sandwich arrangement, as will be realized by those familiar in the high frequency design art, maximizes capacitance to improve the high frequency performance of the resulting IC.
Signal plane 78 resides at the top surface of wafer board 56 and comprises a plurality of conducting leads radiating outwardly from the die end, i.e. left to right in FIG. 2B. The conducting leads are electrically coupled at their outer, i.e., right, ends with inwardly-extending fingers 66 of leadframe 68. The conducting leads are further electrically coupled at their inner, i.e., left, ends with bonding pads on the top surface of die 10 using wires 64 (shown in FIG. 1).
Some of the wires 64 are also used to couple die bonding pads to ground I/O plane 74 and Vdd I/O plane 76. A solder mask structure 77 is provided to keep these two planes from being shorted together by wires 64. Within ground I/O plane 76, conductors are strategically placed, e.g., a ground I/O conductor under every five conducting leads, so as to minimize the inductance and the concomitant crosstalk experienced by the conducting leads in signal plane 78.
As it stands, the ETEQFP of FIG. 2A represents a low-cost and highly efficient structure for attaching a high performance IC die to a leadframe while maximizing high electrical and thermal performance. When the ETEQFP of FIG. 2A is placed in a mold for encapsulation, however, it is discovered the above-discussed pinhole and warpage problems may sometimes occur. This is because both wafer board 56 and thermally conductive heat sink 54 are disposed on one side of the leadframe. In other words, when leadframe 68 is clamped between two halves of a mold, e.g., mold 24 of FIG. 1, the cavity half in which wafer board 56 and heat sink 54 are positioned present a reduced flow cross-section to the injected molten mold material, thereby reducing its flow rate relative to that in the other cavity half. As illustrated in FIG. 3, the imbalance in the flow of the molten mold material (shown by the arrows) plugs the exhaust vent, traps air in the lower cavity half and results in pinholes, of which pinhole 102 is exemplary.
Further, the fact that both the wafer board and the heat sink are positioned in one mold cavity half means that less molten mold material is present in that mold cavity half relative to the other mold cavity half. When the molten mold material cools, the side of the finished IC with less mold material, i.e., the heat sink side, tends to shrink less, resulting in warpage of the finished IC product as illustrated in FIG. 4.
In view of the foregoing, what is desired is improved methods and apparatuses for encapsulating thermally enhanced (TE) and electrically and thermally enhanced (ETE) integrated circuit assemblies that include bulky thermally conductive heat sinks so as to prevent the formation of pinholes and IC warpage.